Low power design is a major issue in integrated circuit design. With the continuous scaling of technology, increased die area and faster clock speeds, the power consumption of on-chip interconnects is very significant.
Long on-chip interconnects are one of the main bottlenecks in microprocessor design due to the impact of coupling capacitance on both interconnect (or bus) delay and power dissipation. For example, in deep submicron technology, the aspect ratio may be over 2.0 for intermediate wiring layers. This indicates that the lateral component of the interconnect capacitance (i.e., coupling capacitance) continually grow to dominate the total interconnect capacitance due to reduction in wire pitch and an increase in the aspect ratio of the interconnect. Lateral interconnect capacitance components are from three to five times as much as vertical capacitance components. Architectures should be designed to reduce the impact of the coupling capacitance on energy dissipation and delay of on-chip interconnects.
Introducing a relative delay between adjacent lines reduces the maximum effective coupling capacitance by approximately half which leads to a considerable reduction in the maximum total capacitance and hence bus delay. Techniques may introduce a relative delay between oppositely switching lines to reduce interconnect delays and increase bus performance. A delay may be introduced by adding extra buffers on alternate bus lines, or skewing the inverters to change the rise and fall delays of the repeaters. On average, if a relative delay is permanently introduced between any two adjacent lines, then the average energy dissipation of the bus will not change.